The invention relates to diffusion barrier layers and methods therefor, particularly, diffusion barrier layers for micro-electronic fluid ejecting devices such as used in ink jet printheads which contain aluminum metallization layers.
In a semiconductor chip containing transistor devices, metal layers function to electrically interconnect the device""s different components to one another. Such metal layers generally comprise contacts, which connect the metal layer to the transistor devices and other metal layers, and traces. Aluminum has long been a preferred material for forming the metal interconnect layers, because it is relatively inexpensive and easy to work with.
Unfortunately, aluminum interconnect layers often create problems with the devices formed in a semiconductor chip made of silicon if the device undergoes temperatures in excess of about 400xc2x0 C. during manufacture of the device. For example, when the aluminum is deposited on a silicon surface the two materials tend to intermix to some degree at their interface. The solubility of silicon in aluminum increases with increasing metallization temperature and approaches about 1 weight percent at about 500xc2x0 C. as shown by a aluminum silicon phase diagram in FIG. 1. At about 500xc2x0 C., silicon readily diffuses into aluminum in order to satisfy its solubility requirement. The loss of silicon from the substrate leaves pits behind in the substrate. Likewise, aluminum counter-migrates into the silicon substrate during subsequent deposition or anneal processes. Since very small amounts of aluminum dissolve in silicon, the migrated aluminum fills the silicon depleted regions or pits and forms aluminum filaments. The condition wherein aluminum has migrated into the silicon is known as xe2x80x9cspiking.xe2x80x9d Spiking can create short circuits in the device when the migrated aluminum spikes through an active region in the silicon device. The aluminum spikes can short a reverse-biased junction and cause a short or excessive leakage of the device.
In order to reduce or prevent aluminum junction spiking problems, the diffusion of silicon into aluminum and vice versa should be minimized. A diffusion barrier layer is typically used to reduce migration of silicon and aluminum into each other. However, providing a diffusion barrier significantly increases the manufacturing costs for micro-electronic devices because multiple steps are often required to pattern and etch the diffusion barrier layer. Since the diffusion barrier layer is usually highly conductive, it must be etched prior to depositing a resistive layer in order to prevent shorting between other devices such as resistors deposited on the semiconductor substrate. There is a need therefore, for improved techniques and processes for reducing spiking caused by diffusion between aluminum and silicon during a semiconductor chip manufacturing process without increasing the number of processing steps required for making such chips.
With regard to the foregoing and other objects and advantages the invention provides a semiconductor device containing at least one transistor and at least one heater resistor in a heater resistor area adjacent the at least one transistor on a semiconductor substrate. The device includes a silicon substrate containing contact openings for metal contacts to the at least one transistor. A barrier layer is adjacent the contact openings and provides a diffusion barrier/heater resistor layer. The barrier layer is selected from a group consisting of TaN, Ta/TaAl, TaN/TaAl, TiWN, TaAlN, TiN, Ta(Nx, Oy), WSi(Nx, Oy), TaSi, TaSiN, WSiN, and TaSi(Nx, Oy). A conductive layer is adjacent at least a portion of the barrier layer for providing connection between a power source and the at least one heater resistor and at least one transistor. The semiconductor device is devoid of a patterned and etched barrier layer in the heater resistor area.
In another aspect the invention provides a method for reducing spiking in a semiconductor device undergoing a process temperature in excess of about 400xc2x0 C. during a process step therefor and containing at least one transistor and at least one heater resistor in a heater resistor area adjacent the transistor on a silicon semiconductor substrate. The method includes the steps of providing contact openings adjacent at least the one transistor for metal contacts to the at least one transistor. A diffusion barrier/resistive layer is deposited in the contact openings and in the heater resistor area. The barrier/resistive layer is selected from the group consisting of TaN, Ta/TaAl, TaN/TaAl, TiWN, TaAlN, TiN, Ta(Nx, Oy), WSi(Nx, Oy), TaSi, TaSiN, WSiN, and TaSi(Nx, Oy). A conductive layer is deposited on the barrier/resistive layer to provide connection between a power source and the at least one heater resistor and at least one transistor. According to the method a step of patterning and etching a barrier layer in the heater resistor area prior to depositing a resistive layer is avoided.
An advantage of the invention is that it provides a semiconductor device such as a printhead heater chip containing one or more transistors and heater resistors having improved resistance to junction spiking without the need for separate diffusion barrier and resistive layers. For example, conventional diffusion barrier layers such as TiW cannot be used as a resistive layer because they are too conductive. Accordingly, the TiW layer is preferably removed, as by an etching step, from the heater resistor area of an ink jet heater chip. After removing the TiW layer, a separate heater resistor layer is deposited on the surface of the chip followed by a conductive layer. Because the diffusion barrier layer or composite diffusion barrier layer is selected from or includes a resistive material, according to the invention, a separate step of etching the diffusion barrier layer in a heater resistor area prior to depositing the heater resistor layer is eliminated. The invention is particularly applicable to a semiconductor device containing at least one transistor and an adjacent heater resistor, wherein the device undergoes a temperature excursion in excess of about 400xc2x0 C. during a process step for manufacturing the semiconductor device.